The present invention relates to a semiconductor device, in particular to a semiconductor memory device having SRAM (Static Random Access Memory) cells.
Patent Literature 1 discloses a technology for, when something is written to some of plural SRAM cells coupled to an identical word line, attaining simultaneously both the stabilization of write operation to the relevant SRAM cells and the speed-up of read operation and the prevention of malfunction in SRAM cells not subjected to writing (namely SRAM cells subjected to reading). FIG. 20 shows the configuration of an SRAM cell disclosed in Patent Literature 1 for attaining the above objects. An SRAM cell 900 shown in FIG. 20 has a pair of inverters constituting a flip-flop circuit. The inverter pair includes a first complementary metal oxide semiconductor (CMOS) inverter having transistors NM1 and PM1 and a second CMOS inverter having transistors NM2 and PM2.
Further, the SRAM cell 900 shown in FIG. 20 has a feed control switch P3 and a capacitive element C1. The feed control switch P3 is arranged between a feed node NDD of the inverter pair and a high reference voltage VDD. The feed control switch P3 is turned off when a word line WL is in a selective state (namely a HIGH potential) and disconnects the feed node NDD from the high reference voltage VDD. Meanwhile, the capacitive element C1 is arranged so as to have an electrostatic capacitance between the feed node and the word line WL. The capacitive element C1 raises the voltage of the feed node NDD disconnected from the high reference voltage VDD by the switch P3.
Data write operation to the SRAM cell 900 shown in FIG. 20 is as follows. That is, in a cell where rewriting is performed, the potential of the feed node NDD comes to be a level lower than the high reference voltage VDD when the word line WL is selected and the potential of the word line WL shifts from a LOW level to a HIGH level. As a result, bit inversion of the cell where the rewriting is performed is facilitated and the write margin improves. Meanwhile, in a cell, where rewriting is not performed, coupled to the word line WL identical to the cell subjected to rewriting, the potential of the feed node NDD is retained at a level higher than the high reference voltage VDD when the potential of the word line WL shifts from the LOW level to the HIGH level. As a result, bit inversion (namely data destruction) hardly occurs in the cell not subjected to rewriting.
Meanwhile, data read operation from the SRAM cell 900 shown in FIG. 20 is as follows. That is, in a cell where reading is performed, the potential of the feed node NDD of the inverter pair rises to a level higher than the high reference voltage VDD when the word line WL is selected and the potential of the word line WL shifts from the LOW level to the HIGH level. As a result, the voltage of a first memory node (here a memory node NA) retaining the HIGH level comes to be a level higher than the high reference voltage VDD and the drivability of a second drive transistor (NM2) to drive a second memory node (NB) retaining the LOW level improves. Consequently, the electricity charged in a bit line (BL_B) is discharged rapidly through a second transfer transistor (NM4) and the second drive transistor (NM2) and the potential rise of the second memory node (NB) of the LOW potential is suppressed. As a result, the SRAM cell 900 shown in FIG. 20 can improve an SNM (Static Noise Margin) during reading and can contribute to the increase of a read speed. In a non-read cell coupled to the word line WL identical to the cell subjected to reading too, the potential of the feed node NDD is retained at a level higher than the high reference voltage VDD. As a result, bit inversion (namely data destruction) of the non-read cell hardly occurs.
Patent Literature 2 discloses a configuration in which a MOS transistor operating as a capacitive element is coupled to a memory node of an SRAM cell. Specifically, the gate of the MOS transistor operating as a capacitive element is coupled to the memory node. Further, the source and drain of the MOS transistor operating as a capacitive element are coupled to a high reference voltage VDD, a low reference voltage (ground voltage GND), or the memory node. By such a configuration, the SRAM cell disclosed in Patent Literature 2 can add the electrostatic capacitance corresponding to the gate capacitance of the MOS transistor operating as a capacitive element to the memory node. As a result, the SRAM cell of Patent Literature 2 can contribute to the improvement of soft error resistance.    Patent Literature 1: Japanese Unexamined Patent Application Publication No. 2007-200520    Patent Literature 2: Japanese Unexamined Patent Application Publication No. 2002-050183